1. Field of the Invention
The present invention relates to a memory system, and, in particular, to a memory system having an improved data bus topology and/or control signal topology. Moreover, the present invention relates to a memory subsystem for such a memory system.
2. Description of Prior Art
One conventional memory system which is implemented nowadays in a wide spread manner is the DDR1 memory subsystem.
In a DDR1 memory subsystem, a memory controller and a number of slots are arranged on a memory board. The slots are for receiving connectors of DDR DRAM modules. The DDR DRAM modules include a module board and respective memory chips arranged on the module board. Signal buses are provided for transferring signals between the memory chips and the controller, i.e. for transferring clock signals, data signals and control signals therebetween. The control signals are typically C/A signals (C/A=command/address).
In the following, bus topologies of the DDR1 memory subsystem and of the successor thereof, i.e. the DDR2 memory subsystem, are set out making reference to FIG. 11 to 13a. 
FIG. 11 schematically shows the data bus topology of the DDR1/DDR2 memory subsystem. A memory controller 10 is arranged on a circuit board (not shown) of the memory subsystem. A data bus 12 is arranged on the circuit board and connected to the controller 10. In addition, the data bus 12 is connected to slot connectors 13 having respective slots for receiving DDR1/DDR2 memory modules 14. On the modules 14, i.e. the module board thereof, respective data lines 16 are arranged which connect DDR DRAM chips 18 arranged on the module boards to the data bus 12. Moreover, the data bus 12 is connected to a reference potential via a termination resistor 20 at the end opposite to the memory controller 10.
Thus, in existing DDR1/DDR2 memory subsystems, the data bus topology includes a linear data bus 12 on the circuit board (or motherboard) of the memory system and stub buses 16 to the memory chips 18 arranged on the memory modules 14.
A unbuffered clock topology for DDR1/DDR2 memory systems is shown in FIG. 12a. For sake of simplicity, differential traces are shown like single ended once in FIG. 12a. As can be seen in FIG. 12a, the controller 10 is connected to a phase locked loop 22 (PLL) via a clock line 24. The phase locked loop 22 generates clock signals on a plurality of twelve clock sublines 26. Respectively, three clock sublines 26 are connected to each of the memory modules 14, which are received in slots 1 to 4 as it is indicated in FIG. 12a. In FIG. 12a, the memory module inserted into slot 1 is shown as having nine DDR DRAM chips 18. The memory modules inserted in slots 2 to 4 are not drawn to this detail. Moreover, each clock subline 26 branches into three clock sub-sublines 28 each of which is connected to a respective memory chip 18. PLL feedback traces are not shown in the figures. Although four modules for the unbuffered clock topology are shown in FIG. 9a, usually no more than three modules are used in PC desktop systems.
In the clock bus topology shown in FIG. 12a, one part of the clock sublines 26 is formed on the memory board and one part thereof is formed on the module board. Both parts are connected via the slot connector into which the memory module is inserted. The clock sub-sublines 28 are formed on the memory boards. In the unbuffered clock topology shown in FIG. 12a, clock signals must be simultaneously delivered to all DRAM chips.
A registered clock topology for DDR1/DDR2 memory systems is shown in FIG. 12b. 
In this topology, a phase locked loop 30 is provided on the respective memory modules 14. The memory controller 10 is connected to the phase locked loops 30 of the memory modules 14 by a respective clock line 32. The phase locked loop 30 comprises a number of output lines 34 corresponding to the number of memory chips 18. In the clock topology shown in FIG. 12b, runtime differences due to different lengths of the clock lines 32 can be equalized by the phase locked loops 30.
An unbuffered bus topology for C/A buses of the DDR1/DDR2 memory system is shown in FIG. 13a, whereas a registered bus topology for the C/A buses of a DDR1/DDR2 memory system is shown in FIG. 13b. 
In the unbuffered C/A bus topology, a C/A bus 40 is provided on the memory circuit board and connected to a reference potential by a termination resistor 42. A common C/A bus portion 44 of the respective memory modules 14 is connected to the C/A bus 40 via respective slot connectors 45. The common C/A bus portion 44 branches in C/A subbuses 46 each of which is connected to a respective DDR DRAM chip 18. In FIG. 13a, only one address line of the C/A bus topology is shown, whereas, in reality, a plurality of 21 to 27 address lines may be provided.
In the registered C/A bus topology shown in FIG. 13b, each of the memory modules 14 comprises a register 50 which is connected to a C/A bus 52 on the memory circuit board via the slot connectors 45. Again, the C/A bus 52 is connected to a reference potential via a termination resistor 54 at the end opposite to the memory controller 10.
The inventors have recognized that the signal quality in a DDR2 system having four slots and operating at a data rate of 533 Mb/s is not acceptable in case of using a data bus topology like in a DDR1 memory subsystem shown above making reference to FIG. 11.